This invention relates to a device for organizing the accesses, or arbitrating the access requests, to a bus linked to a shared memory. The invention more specifically applies to implementing such a device for managing the access priorities to this bus between a microprocessor and different entities needing access to the memory.
The present invention aims at organizing the accesses to the bus without it being necessary to use the microprocessor and by using all the potential read or write cycles in case of a surge of requests.
The present invention also aims at avoiding the monopolizing of the bus by an entity while other entities request access to the bus.
The present invention also aims at enabling the sharing of the bus between several devices of the same type associated with a same microprocessor and a same memory.
To achieve these objects, the present invention provides a device for organizing the access to a bus connecting a memory to at least two entities issuing asynchronous binary signals representing requests for access to the bus, the device issuing binary signals for authorizing the access to the bus by these entities based on a determination of the priority between the different requests and including a priority decoder in wired logic associated with an input register, a loading of the state of the access request signals into the input register occurring, when an access request is present while a read or write cycle of the memory is executed, upon the arrival of a pulse on a signal indicative of the end of a memory cycle and issued by a memory controller constituting an electric interface between the bus and the memory.
In the context of the present invention, a memory controller is a device constituting an electric interface between the bus and the physical memory. This interface does not carry out any address calculation. It only transfers the addresses, the data and the control signals to the memory by achieving, if necessary, a multiplexing of the addresses. The memory controller does not identify the entity from which it receives the data and the addresses.
According to an embodiment of the present invention, the signal indicative of the end of a memory cycle is sent by the memory controller in advance with respect to the actual end of the memory cycle, by a delay which is a function of the access request processing time of the priority decoder.
According to an embodiment of the present invention, the device includes a programmable register containing codes for identifying the entities, a location of each code in the programmable register determining the priority rank assigned to the entity associated with the code and the programmable register being read by the priority decoder as the loading of the state of the access request signals in the input register is triggered.
According to an embodiment of the present invention, the loading of the state of the access request signals in the input register is controlled by a signal representing a logic combination taking into account the signal indicative of the end of the memory cycle and a first clock signal.
According to an embodiment of the present invention, the priority decoder sends to the memory controller a binary signal indicative of the presence of an authorized access request, the state of said binary signal being switched to an active state by the presence of an authorized access request and, to an idle state, by the arrival of a pulse on the signal indicative of the end of the memory cycle.
According to an embodiment of the present invention, the signal for controlling the input register takes into account the state of the signal indicative of the presence of an authorized access request.
According to an embodiment of the present invention, one of the entities sends periodic access requests and has a specific priority management scheme which includes assigning a lowest priority rank thereto for one half-period of a time interval which separates two of its access requests and a highest priority rank for a second half-period of the interval when its access request has not been answered in the first half-period.
According to an embodiment of the present invention, the memory is a dynamic memory, the entity with the specific priority management scheme including a circuit for refreshing the dynamic memory.
According to an embodiment of the present invention, one of the entities includes a microprocessor.
According to an embodiment of the present invention, the device includes means for connecting other devices of a same type to organize a sharing of the memory between several groups of entities, the assignment of the bus to one of the groups of entities being performed by circulating a pulse, or xe2x80x9ctokenxe2x80x9d, in a single wire line connecting the different devices in a ring, each device receiving the xe2x80x9ctokenxe2x80x9d as an input signal sent by a preceding device as an output signal.
According to an embodiment of the present invention, said connecting means include a device for regenerating the xe2x80x9ctokenxe2x80x9d by using flip-flops controlled by a second clock signal and logic gates, the regenerating device receiving, besides the input signal, a binary signal indicative of the existence of an access request within the group associated therewith and issuing, to the priority decoder of the device associated therewith, a binary signal indicative of an assignment of the xe2x80x9ctokenxe2x80x9d to the device, the width of the pulse which constitutes the xe2x80x9ctokenxe2x80x9d corresponding to one period of the second clock signal.
According to an embodiment of the present invention, the sending of the xe2x80x9ctokenxe2x80x9d by the regenerating device as the output signal is triggered either by the arrival of the signal indicative of the end of a memory cycle or by the absence of access requests from the entities of the group associated therewith while the xe2x80x9ctokenxe2x80x9d is present on the input signal, the sending of the xe2x80x9ctokenxe2x80x9d being synchronous with the second clock signal.
According to an embodiment of the present invention, the control signal of the input register of a device is enabled by the signal indicative of an assignment of the xe2x80x9ctokenxe2x80x9d to the device.
According to an embodiment of the present invention, said means include a device for initially generating the xe2x80x9ctokenxe2x80x9d under control of a bit, the generating device issuing a signal for switching the regeneration device between a ring operation and a local mode operation where it permanently holds the right to authorize an access to the bus.
These objects, features and advantages, as well as others, of the present invention will be discussed in detail in the following description of specific embodiments, taken in conjunction with the following drawings, but not limited by them.